Presenting a project in an international forum can be an exhilarating experience for a student. It is a moment of pride and accomplishment to showcase their hard work and research to a global audience. The opportunity to present in such a prestigious setting provides a sense of validation and recognition for their efforts. It offers a platform to share their innovative ideas, gain exposure to diverse perspectives, and receive valuable feedback from experts in the field.
Raghava S N pursuing an iMTech degree in electronics and communications. His background is working on ML problems and trying to solve them using hardware optimization and acceleration using FPGAs, GPUs etc. Raghava did a project under the guidance of Prof. Nanditha Rao which he presented recently at the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) Demo Night, 2023 in Los Angeles. The event stands as a premier platform where groundbreaking research centered around computing that harnesses the unique capabilities of FPGAs and other reconfigurable hardware is presented and discussed. The Demo Night takes center stage, offering a casual environment for all conference attendees to mingle and exchange knowledge. This event serves as a platform for showcasing system designs, platforms, tools and more.
The project which Raghava presented at Demo Night is a vectored systolic array generator designed to perform 2D convolution on FPGAs. The entire basis of computer vision is 2D Convolution and our project aims to accelerate this process by leveraging the high data and algorithm-level parallelism offered by FPGAs. Giving further details on the project, he says, “A systolic array is a structure that uses parallel patterns in data to compute on two or more different data points at the same time. This is done by a unit called the processing element(PE) inside the systolic array. The building blocks of 2D convolution is the multiply and accumulate operation(MAC), which can be efficiently done by systolic Arrays for vectors(hence vectored systolic array). This is because each element of a vector is independent of each others and can undergo computations parallelly. Say there are 3 vectors a, b and c each of size 10. The mac operation calculates a*b +c. By using the vector systolic array, we can obtain the result of the mac operation in 1 clock cycle (In one go all 10 elements of the result are obtained) instead of waiting for 10 clock cycles, each giving 1 element of the resultant vector.”
Much delighted, Raghava says, “The Demo Night was a great opportunity for me to exhibit my research work, demonstrate the usage of it and receive valuable early feedback on their ongoing projects. It was an amazing experience for me, as I met many distinguished scholars in the field of customized computing, which is quite a niche field. I made many connections and saw first-hand the cutting-edge research that is done all around the world. I also received a lot of positive feedback for our project and presentation. I was the only presenter at the conference who was still doing my undergraduate degree and a lot of people were surprised by that! They commended the research work the college does and some of them hoped to collaborate with us as well.”
Raghava expresses his gratitude towards IIIT Bangalore for providing support in terms of partial financial assistance and encouragement. He also acknowledges Prof. Nanditha Rao as an exceptional mentor and expresses appreciation for the assistance he received from his senior, Veerendra Devaraddi, who had previously worked on the same project. Raghava hopes to witness his peers presenting their work in similarly prestigious forums. Furthermore, he thoroughly enjoyed exploring Los Angeles for a day.